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a615308 series preliminary 32k x 8 bit high speed cmos sram preliminary ( june, 1998, version 1.1) amic technology, inc. document title 32k x 8 bit high speed cmos sram revision history rev. no. history issue date remark 1.0 initial issue march 12, 1998 1.1 modify 28-pin tsop package outline drawing and dimensions june 17, 1998
a615308 series preliminary 32k x 8 bit high speed cmos sram preliminary ( june, 1998, version 1.1) 1 amic technology, inc. features n single +5v power supply n access times: 10/12 ns (max.) n current: operating: 150ma (max.) standby: 12ma (max.) n full static operation, no clock or refreshing required n all inputs and outputs are directly ttl compatible n common i/o usi ng three-state output n data retention voltage: 2v (min.) n available in 28-pin soj and tsop packages general description the a615308 is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 5v power supply. it is built using high performance cmos process. inputs and three-state outputs are ttl compatible and allow for direct interfacing with common system bus structures. minimum standby power is drawn by this device when ce is at a high level, independent of the other input levels. data retention is guaranteed at a power supply voltage as low as 2v. pin configurations n soj n tsop a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce oe a11 a9 a8 a13 we vcc a10 a615308 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a615308 1 9 28 20 a11 2 3 4 5 6 7 8 10 11 12 13 14 a9 a8 a13 a14 a12 a7 a6 a5 a4 a3 27 26 25 24 23 22 21 19 18 17 16 15 i/o 6 i/o 5 i/o 4 i/o 3 gnd i/o 2 i/o 1 i/o 0 a0 a1 a2 a10 vcc i/o 7 oe we ce ~ ~ ~ ~
a615308 series preliminary (june, 1998, version 1.1) 2 amic technology, inc. block diagram row decoder 256 x 1024 memory array input data circuit column i/o column decoder control circuit we i/o 7 i/o 0 a14 a8 a7 a4 a0 a11 vcc gnd a10 oe a5 ce a9 a3 a6 a12 a13 a1 a2 pin descriptions - skinny/soj pin no. symbol description 1 - 10, 21, 23 - 26 a0 - a14 address inputs 11 - 13, 15 - 19 i/o 0 - i/o 7 data inputs/outputs 14 gnd ground 20 ce chip enable 22 oe output enable 27 we write enable 28 vcc power supply pin description - tsop pin no. symbol description 1 oe output enable 2 - 5, 8 - 17, 28 a0 - a14 address input 6 we write enable 7 vcc power supply 18 - 20, 22 - 26 i/o 0 - i/o 7 data inputs/outputs 21 gnd ground 27 ce chip enable
a615308 series preliminary (june, 1998, version 1.1) 3 amic technology, inc. recommended dc operating conditions (t a = 0 c to + 70 c) symbol parameter min. typ. max. unit vcc supply voltage 4.5 5 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 3.5 vcc + 0.3 v v il input low (1) voltage -0.5 0 +0.8 v c l output load - - 30 pf absolute maximum ratings* vcc to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +5.5v in, in/out volt to gnd . . . . . . . . . . -0.5v to vcc +0.5v operating temperature, topr . . . . . . . . . . . 0 c to +70 c storage temperature, tstg . . . . . . . . . . -55 c to +125 c temperature under bias, tbias . . . . . . . . -10 c to +85 c power dissipation, p t . . . . . . . . . . . . . . . . . . . . . . . 1.0w *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = 0 c to + 70 c, vcc = 5v 10%, gnd = 0v) symbol parameter a615308-8/10/12 unit conditions min. max. ? i li ? input leakage - 2 m a v in = gnd to vcc ? i lo ? output leakage - 2 m a ce = v ih or oe = v ih v i/o = gnd to vcc i cc1 (2) dynamic operating current - 150 ma ce = v il , i i/o = 0 ma min. cycle, duty = 100% i sb - 35 ma ce = v ih i sb1 standby power supply current - 12 ma ce 3 vcc - 0.2v v in 3 vcc -0.2v or v in 0.2v v ol output low voltage - 0.4 v i ol = 8 ma v oh output high voltage 2.4 - v i oh = -4 ma notes: 1. v il = -3.0v for pulses less than 20 ns. 2. i cc1 is dependent on output loading, cycle rates, and read/write patterns.
a615308 series preliminary (june, 1998, version 1.1) 4 amic technology, inc. truth table mode ce oe we i/o operation supply current standby h x x high z i sb , i sb1 output disable l h h high z i cc1 read l l h d out i cc1 write l x l d in i cc1 note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 10 pf v in = 0v c i/o * input/output capacitance 10 pf v i/o = 0v * these parameters are sampled and not 100% tested. ac characteristics (t a = 0 c to +70 c, vcc = 5v 10%) symbol parameter a615308-10 a615308-12 unit min. max. min. max. read cycle t rc read cycle time 10 - 12 - ns t aa address access time - 10 - 12 ns t ace chip enable access time - 10 - 12 ns t oe output enable to output valid - 5 - 6 ns t clz chip enable to output in low z 3 - 3 - ns t olz output enable to output in low z 0 - 0 - ns t chz chip disable output in high z 0 5 0 6 ns t ohz output disable to output in high z 0 5 0 6 ns t oh output hold from address change 3 - 3 - ns
a615308 series preliminary (june, 1998, version 1.1) 5 amic technology, inc. ac characteristics (continued) symbol parameter a615308-10 a615308-12 unit min. max. min. max. write cycle t wc write cycle time 10 - 12 - ns t cw chip enable to end of write 9 - 10 - ns t as address setup time of write 0 - 0 - ns t aw address valid to end of write 9 - 10 - ns t wp write pulse width 9 - 10 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z 0 5 0 6 ns t dw data to write time overlap 5 - 6 - ns t dh data hold from write time 0 - 0 - ns t ow output active from end of write 3 - 3 - ns notes: t chz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levles. timing waveforms read cycle 1 (1) t rc address d out t aa t oe t olz 5 t ace t clz 5 t chz 5 t oh oe t ohz 5 ce
a615308 series preliminary (june, 1998, version 1.1) 6 amic technology, inc. timing waveforms (continued) read cycle 2 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 3 (1, 3, 4,) t clz 5 t ace t chz 5 d out ce notes: 1. we is high for read cycle. 2. device is continuously enabled, ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 200mv from steady state. this parameter is sampled and not 100% tested.
a615308 series preliminary (june, 1998, version 1.1) 7 amic technology, inc. timing waveforms (continued) write cycle 1 (6) (write enable controlled) t wc address d in t ow 7 t dh t dw t whz 7 t wp 2 t as 1 (4) t cw 5 t aw t wr 3 d out we ce write cycle 2 (chip enable controlled) t wc address d in t dw t whz 7 t aw t wr 3 d out t dh (4) t wp 2 t cw 5 t as 1 ce we notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap ( t wp ) of a low ce and a low we . 3. t wr is measured from the earliest of ce or we going high to the end of the write cycle 4. if the ce low transition occurs simultaneously with the we low transition or after the we transition, outputs rem ain in a high impedance state. 5. t cw is measured from the later of ce going low to the end of write. 6. oe is continuously low. ( oe = v il ) 7. transition is measured 200mv from steady state. this parameter is sampled and not 100% tested.
a615308 series preliminary (june, 1998, version 1.1) 8 amic technology, inc. ac test conditions input pulse levels 0v to 3.0v input rise and fall time 2 ns input and output timing reference levels 1.5v output load see figures 1 and 2 +5v i/o 255 w 480 w 5pf* * including scope and jig. z o =50 w output r l =50 w v t =1.5v figure 1. ou tput load figure 2. output load for t clz , t olz , t chz , t ohz , t whz , and t ow data retention characteristics (t a = 0 c to 70 c) symbol parameter min. max. unit conditions v dr vcc for data retention 2 5.5 v ce 3 vcc - 0.2v i ccdr data retention current - 6 ma vcc = 2.0v ce 3 vcc - 0.2v v in 3 vcc - 0.2v or v in 0.2v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time t rc * - ns t rc = read cycle time
a615308 series preliminary (june, 1998, version 1.1) 9 amic technology, inc. low vcc data retention waveform vcc ce t cdr v ih 4.5v t r v ih 4.5v data retention mode v dr 3 2.0v ce 3 v dr - 0.2v ordering information part no. access time ( ns) operating current max. ( ma) standby current max. ( ma) package A615308S-10 10 150 12 28l soj a615308s-12 12 150 12 28l soj a615308v-10 10 150 12 28l tsop a615308v-12 12 150 12 28l tsop
a615308 series preliminary (june, 1998, version 1.1) 10 amic technology, inc. package information soj 28l outline dimensions unit: inches/mm 1 e h e a 1 a 2 a e e 1 c 14 15 28 s d seating plane d y l b 1 b dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.140 - - 3.56 a 1 0.027 - - 0.69 - - a 2 0.095 0.100 0.105 2.41 2.54 2.67 b 1 0.028 typ 0.71 typ b 0.018 typ 0.46 typ c 0.010 typ 0.25 typ d - 0.710 0.730 - 18.03 18.54 e 0.295 0.300 0.305 7.49 7.62 7.75 e 0.050 bsc 1.27 bsc e 1 0.255 0.265 0.275 6.48 6.73 6.99 h e 0.329 0.337 0.345 8.36 8.56 8.76 l 0.077 0.087 0.097 1.96 2.21 2.46 s - - 0.045 - - 1.14 y - - 0.004 - - 0.10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
a615308 series preliminary (june, 1998, version 1.1) 11 amic technology, inc. package information tsop 28l type i (8 x 13.4mm) outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.049 - - 1.25 a 1 0.002 - - 0.05 - - a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.005 - 0.008 0.12 - 0.21 e 0.311 0.315 0.319 7.90 8.00 8.10 l 0.012 0.020 0.028 0.30 0.50 0.70 d 0.520 0.528 0.536 13.20 13.40 13.60 d 1 0.461 0.465 0.469 11.70 11.80 11.90 e 0.022 bsc 0.55 bsc s 0.017 typ 0.425 typ y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. the maximum value of dimension d 1 includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash. d 1 e e d l a a 2 c detail "a" d y detail "a" s a 1 b 28 15 1 14 q

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